Reduction Of Architecture Vulnerability Factor Using Modified Razor Flipflops

Research has shown that microprocessors and structures of the microprocessors are vulnerable to alpha Single Event Upsets that affect program correctness and reliability. In this thesis, we have explored the use of Modified Razor flip-flops in the microprocessor to increase the overall reliability of the microprocessor. We have adopted Architecturally Correct Execution (ACE)…


1 Introduction
1.1 Soft Errors and Single Event Upsets
1.2 Reliability, Vulnerability and Quantifying Vulnerability
1.3 Reducing Architecture Vulnerability Factor
1.4 Our Contribution
1.5 Organization of the Thesis
2 Soft Errors and Architecture Vulnerability Factor
2.1 Overview
2.2 Soft Errors and Impact on Industry
2.3 Silent Data Corruption and Detected Unrecoverable Errors
2.4 Measuring Soft Error Rates
2.5 Architecture Vulnerability Factor
3 Computation of Architecture Vulnerability Factor
3.1 Overview
3.2 ACE Bits and AVF
3.3 Identifying Control Path ACE and Non-ACE bits
3.4 Identifying Data Path ACE and Non-ACE Bits
3.5 Computation of ACE Time and AVF
4 Modified Razor Flip-Flops
4.1 Razor Flip-flops: Background
4.2 Modified Razor flip-flops
4.3 Reduction in AVF
4.4 Power and Area Overhead
5 Experimental Results
5.1 Simulation Model
5.2 RTL Models
5.3 AVF and ACE Time
5.4 Reduction in AVF with Modified Razor flip-flops
5.5 Increase in Area and Power
5.6 Cost effective Percentage decrease in AVF
5.7 Observations
6 Summary and Conclusion
6.1 Summary
6.2 Conclusion

Author: Seshadri, Kiran Kalkunte

Source: University of Maryland

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