This thesis study involves designing, implementing and testing of a novel radio resource control algorithm for the closed loop power control in the LTE uplink. Different values of the path loss compensation factor are investigated in the range 0.7-1.0 and an optimal value of 0.8 as allowed by the LTE standard is proposed. Both the ideal and a more realistic case modeled by including delay, error, and power headroom reporting were studied.Simulation results indicated that the closed loop power control with fractional path loss compensation factor is advantageous compared to closed loop power control…
Contents
CHAPTER 1 INTRODUCTION
1.1 THESIS OBJECTIVE
1.2 THESIS SCOPE
1.3 ASSESSMENT METHODOLOGY
1.4 THESIS OUTLINE
CHAPTER 2 BACKGROUND
2.1 WIRELESS COMMUNICATION SYSTEM
2.1.1 Radio signal propagation
2.1.1.1 Path loss
2.1.1.2 Shadow fading
2.1.1.3 Multipath fading
2.1.2 Cellular network fundamentals
Cell site
Base station coverage area
Cell
2.1.2.1 Multiple access techniques
2.1.2.2 Coverage
2.1.2.3 Capacity
2.1.2.4 Frequency reuse
2.1.2.5 Interference
2.1.2.6 Signal to noise power ratio
2.2 LONG TERM EVOLUTION – LTE
2.2.1 LTE physical layer
2.2.1.1 Multiplexing Schemes
2.2.1.2 Frame structure
2.2.1.3 Physical resource block
2.2.1.4 Physical uplink shared channel – PUSCH
2.2.1.5 Reference Signals
2.3 ROLE OF POWER CONTROL
2.4 LTE PUSCH POWER CONTROL
2.4 LTE PUSCH POWER CONTROL
2.4.1 PUSCH power control signaling
2.4.2 Power spectral density – PSD
2.4.3 Conventional power control scheme
2.4.4 Fractional power control scheme
2.4.5 Open loop power control
2.4.6 Closed loop power control
HAPTER 3 METHODOLOGY
3.1 PROBLEM FORMULATION
3.2 EVALUATION OF FRACTIONAL OPEN LOOP POWER CONTROL
3.3 IMPLEMENTATION DETAILS OF CONVENTIONAL CLOSED LOOP POWER CONTROL
3.4 IMPLEMENTATION DETAILS OF CLOSED LOOP PC WITH FRACTIONAL PATH LOSS COMPENSATION FACTOR
3.4.1 Power headroom report
3.4.2 Mathematical model for setting SINR target based on path loss of the users
3.5 INVESTIGATING VALUES FOR PATH LOSS COMPENSATION FACTOR
3.6 SINR FILTERING
3.7 DELAY AND ABSOLUTE ERROR MODELS
3.7.1 Processing and round trip time delay model
3.7.2 Absolute error model
CHAPTER 4 RESULTS AND ANALYSIS
1 INVESTIGATION FOR THE OPTIMAL VALUE OF THE PL COMPENSATION FACTOR
2 PERFORMANCE ANALYSIS OF CLOSED LOOP PC USING = 0.8
4.2.1 Ideal case
4.2.2 Performance analysis with absolute error and TPC delay
4.2.3 Performance analysis with power headroom report
4.2.3.1 Performance of power headroom report triggering at periodic intervals only
4.2.3.2 Performance of power headroom report triggering at change in PL only
4.2.3.3 Performance comparison of the power headroom triggers
4.2.4 Performance analysis with power headroom, TPC delay, and absolute error
4.2.5 Power utilization
CHAPTER 5 CONCLUSIONS & FUTURE WORK
5.1 CONCLUSIONS
5.2 FUTURE WORK
Refrences
Appendix A Simulator details
A.1 Path loss and channel models
A.2 Link quality model
A.3 SINR calculations
A.4 BLEP estimation
A.5 Traffic models
A.6 Noise model
A.7 Default simulation parameters
Appendix B Time delay and bit rate calculation
B.1 Processing and round trip time delay
B.2 Bit rate calculation
Appendix C Open loop results
C.1 Performance comparison for different values of the PL compensation factor
C.2 Effect on the performance due to absolute error
Author: Bilal Muhammad
Source: Blekinge Institute of Technology
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