Power Modeling and Scheduling of Tests for Core-based System Chips

The technology today makes it possible to integrate a complete system on a single chip, called “System-on-Chip” (SOC). Nowadays SOC designers use previously designed hardware modules, called cores, together with their user defined logic (UDL), to form a complete system on a single chip. The manufacturing process may result in defect chips, for instance due to the base material, and therefore testing chips after production is important in order to ensure fault-free chips.The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. However, this will result in a higher activity in the chip, hence higher power consumption. Due to several factors in the manufacturing process there are limitations of the power consumption for a chip. Therefore, the power limitations should be carefully considered when planning the testing of a chip. Otherwise it can be damaged during test, due to overheating. This leads to the problem of minimizing testing time under such power constraints.In this thesis we discuss test power modeling and its application to SOC testing…


1 Introduction
1.1 System-on-Chip
1.2 Testing
1.3 Test Power Consumption
1.4 Problem Definition
1.5 Thesis Overview
2 Preliminaries
2.1 Principles of Core-based SOC Testing
2.2 Cores
2.3 Test Architecture Design
2.3.1 Fixed-width Test Bus Architectures
2.3.2 Flexible-width Test Bus Architectures
2.4 Basic Definitions
2.5 Test Time Calculations
3 Related Prior Work
3.1 Wrapper Design
3.2 Test Scheduling
3.3 Test Power Consumption
3.3.1 Power Approximation Models
3.3.2 Test Power Minimization
3.3.3 Power Constrained Test Scheduling
3.4 Power Profile Reshaping
3.5 Summary
4 Power Modeling
4.1 Power Calculation
4.2 Counting Transitions in Shift Registers
4.3 Counting Transitions when Testing Cores
4.4 Test Pattern Reordering
5 Test Scheduling
5.1 The Power Constrained Test Scheduling Problem
5.2 Scheduling with Given Test Architecture
5.3 Scheduling and Test Architecture Design
6 Experiments
6.1 Implementation
6.2 Experiment Setup
6.3 Results
6.3.1 d695
6.3.2 p22810
6.3.3 p93791
6.4 Discussion
7 Conclusions and Future Work
7.1 Conclusions
7.2 FutureWork
List of References

Author: Samii, Soheil

Source: Linkoping University

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