Hardware design of a network address translator

In this thesis a design of Network Address Translator (NAT) for handling flow based translation of Transmission Control Protocol (TCP) for Internet Protocol version 4 (IPv4) is investigated. In flow based the data stream is terminated and restarted on the other side. The design is suited for a hardware implementation which implies several problems. TCP Checksum, TCP Timers, Retransmission, Sliding window and a scalable number of connections are some problems and all have been solved. Other more basic parts of TCP has also been solved and a reasonable TCP standard have been achieved. To implement the design in Hardware Description Language (HDL) to fit into a FPGA has not been achieved. In order to do so, restructuring of some core architecture is needed.

Author: Lundstrom, Stefan

Source: LuleƄ University of Technology

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