Serial protocol engine for USB 1.1 device

USB has become a popular interface for exchanging data between PC’s and peripherals. An increasing number of portable peripherals are using the USB interface to communicate with the PC. The design and implementation of a synthesizable model of the USB 1.1 protocol engine is presented in this report The PHY is compatible with the USB 1.1 transceiver macrocell interface (UTMI) specification and the simulation test confirmed the successful operation of circuits for both full speed (12 Mbps) and low speed (1.5 Mbps) data transmission. the model is written completely in behavioral verilog with a top down approach and the model was verified and validated.


CHAPTER 1 Introduction
1.1 Motivation
1.2 Objective of the Thesis
1.3 Overview of the Task
1.4 Design of the System and Tools Used
1.5 Document Organization
2.1 Shortcoming of Existing PC IO Paradigm
2.1.1 Cable
2.1.2 Installation and Configuration of Expansion Cards
2.1.3 No Hot Pluggability for Peripherals
2.1.4 Cost
2.2 Analysis of Potential Solution
2.2.1 Access Bus
2.2.2 USB — The Right Balance
2.3 USB Features
2.3.1 Plug and Play Support
2.3.2 Hot Attachment
2.3.3 Room for Growth
2.3.4 Low Cost
3.1 USB System Component
3.1.1 USB Device Drivers
3.1.2 USB Driver
3.1.3 USB Host Controller Driver
3.1.5 USB Devices
3.2 USB Communication Model
3.2.1 Communications Flow
3.2.2 Transfers, IRPS, Frames, and Packets Transfers The USB Driver, IRPS and Frames The Host Controller Driver and Transaction
3.3 Device Famework
3.3.1 USB Bus Interface Layer
3.3.2 USB Device Layer
3.3.3 Function layer
3.4 USB Peripheral Connection
3.5 USB Signaling Environment
3.5.1 NRZI Encoding
3.5.3 Differential Pair Signaling
3.6 USB Transfer Types
3.6.1 Interrupt Transfer
3.6.2 Bulk Transfer
3.6.3 Isochronous Transfer
3.6.4 Control Transfer
4.1 Packets – The Basic Building Blocks of USB Transactions
4.1.1 Synchronization Sequence
4.1.2 Packet Identifier
4.1.3 Packet-Specific Information
4.1.4 Cyclic Redundancy Checking (CRC
4.1.5 End of Packet (EOP)
4.2 Packet Types
4.2.1 Token Packets SOF Packet IN Packet OUT Packet SETUP Packet
4.2.2 Data Packets — Data0 and Data1
4.2.3 Handshake Packet
4.3.1 Packet Errors PID Checks CRC Errors Bit Stuff Errors
5.1 Functional Block Diagram
5.2 Implementation Overview
5.2.1 Device Receiver SIE Interfacing Signals
5.2.2 Device Transmitter SIE Interfacing Signals
5.2.3 Digital Phase Locked Loop Interface
5.3 Implementation of Device Receiver SIE
5.3.1 NRZI decoder
5.3.2 Bit Destuffer
5.3.3 Shift Register
5.3.4 Byte Counter
5.3.5 CRC Checker
5.3.6 PID Decoder
5.4 Implementation of Device Transmitter SIE
5.4.1 NRZI Encoder
5.4.2 Bit stuffer
5.4.3 Serial Shifter
5.4.4 Byte Counter
5.4.5 CRC Check Field Generator
5.5 Implementation of Digital Phase Locked Loop
5.5.1 Finite State Machine for End Of Packet Detection
5.5.2 Finite State Machine for Generation of Synchronize Clock
6.1 Simulation Results
6.2 Synthesis Report
7.1 Conclusion
7.2 Future Scope

Author: Guillen, Carlos Alonso

Source: Linkoping University

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