An Integrated System-Level Design for Testability Methodology

HARDWARE TESTING is commonly used to check whether faults exist in a digital system. Much research has been devoted to the development of advanced hardware testing techniques and methods to support design for testability (DFT). However, most existing DFT methods deal only with testability issues at low abstraction levels, while new modelling and design techniques have been developed for design at high abstraction levels due to the increasing complexity of digital systems. The main objective of this thesis is to address test problems faced by the designer at the system level…


I Preliminaries
1 Introduction
1.1 Motivation
1.2 Problem Formulation
1.3 Contributions
1.4 Thesis Overview
2 Background
2.1 Introduction
2.2 Design Representations
2.3 High-Level Synthesis
2.4 Testing and Design for Testability
II Test Scheduling and
Test Access Mechanism Design
3 Introduction and Related Work
3.1 Introduction
3.2 Test Access Mechanism Design
3.3 Test Isolation and Test Access
3.4 Test Scheduling
3.5 Test Set Selection
4 Test Scheduling and
Test Access Mechanism Design
4.1 Introduction
4.2 System Modelling
4.3 Test Scheduling
4.4 Test Floor-planning
4.5 Test Set
4.6 Test Access Mechanism
4.7 The System Test Algorithm
4.8 Simulated Annealing
4.9 Tabu Search
4.10 Conclusions
5 Experimental Results
5.1 Introduction
5.2 Test Scheduling
5.3 Test Access Mechanism Design
5.4 Test Scheduling and
Test Access Mechanism Design
5.5 Test Parallelization
5.6 Test Resource Placement
5.7 Summary
III Testability Analysis and
Enhancement Technique
6 Introduction and Related Work
6.1 Testability Analysis
6.2 Testability Improvement
6.3 Summary
7 Testability Analysis
7.1 Preliminaries
7.2 Behavioral Testability Metrics
7.3 Application of the Behavioral Testability Metrics
7.4 Behavioral Testability Analysis Algorithm
7.5 Experimental Results
7.6 Conclusions
8 Testability Improvement Transformations
8.1 Basic Transformations
8.2 Cost Function for DFT Selection
8.3 Application of the Testability
Improvement Transformations
8.4 Experimental Results
8.5 Variable Dependency
8.6 Conclusions
9 Testability Analysis and
Enhancement of the Controller
9.1 Introduction
9.2 Preliminaries
9.3 Controller Testability Analysis
9.4 State Reachability Analysis Algorithm
9.5 Controller Testability Enhancements
9.6 Experimental Results
9.7 Summary
IV Conclusions and Future Work
10 Conclusions
10.1 Thesis Summery
10.2 Conclusions
11 Future Work
11.1 Estimation of Test Parameters
11.2 Test Scheduling and Test Access Mechanism
11.3 Testability Analysis and
Testability Enhancements
V Appendix
Appendix A
Design Kime
System S
Design Muresan
Extended ASIC Z
System L
Ericsson design

Author: Larsson, Erik

Source: Linköping University

Download URL 2: Visit Now

Leave a Comment