In this project report we will talk about Enhanced Multi Media Adaptor (EMMA). The Internet Protocol (IP) is moving communications into a new era of all-IP integrated systems. Businesses are asking for Voice-over-IP (VoIP) services in order to save costs or perhaps to attain communication convergence. A VoIP gateway is a device which connects analog telephones with an IP-based network. The key tasks of a Voice-over-IP gateway is the translation of the analog telephone signals into a control signaling protocol and also voice packetization. VoIP is surely a rising market where System-on-Chip (SOC) is developed. A SOC is a full system on an integrated circuit (IC) which includes software running on embedded processor cores and hardware intellectual property. In the present day, sellers offer a group of robust tools and intellectual property blocks for developing complete and flexible System-on- Programmable-Chip (SOPC) within a short time.
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This report is dedicated to the development of a low-cost and small VoIP gateway utilizing the SOPC design strategy, and in addition it involves the research of various Power-over-Ethernet (PoE) solutions. This appliance is targeted to be employed as a network test instrument inside enterprise infrastructures. The Altera Cyclone II low-cost FPGA family and Si3210 ProSLIC are picked as the development platforms as this application is focused to moderate volumes of productions, and it cannot afford risks and long design time.
The design flow commences with the explanation of a clear system model, accompanied by hardware and software co-design, and finally prototyping and verification. This design basically makes use of the synergism of software and hardware in the single FPGA platform. The procedures explained in the system model are divided in software and hardware. After that, dedicated digital hardware blocks are put in place with VHDL to speed up voice packetization, while a C/C++ program implements the primary VoIP signaling protocol – Session Initiation Protocol (SIP).
Altera SOPC Builder version 5.0 is utilized to produce the system architecture. The Nios II soft-processor core and group of on-chip peripherals are put together utilizing a flexible interconnection bus structure – the Avalon Switch Fabric. Then, embedded software is created to run over this architecture. It is built and debugged using the Nios II integrated development environment (IDE). Furthermore, the program includes several tasks based on the popular MicroC/OS-II real time operating system (RTOS), that makes use of a lightweight TCP/IP stack (lwIP) to handle network applications.
Ultimately, to be able to validate the system functionality, the system is prototyped with the Altera Nios II Development Board which has a Cyclone II FPGA and the Si321xPPT-EVB. Initially, the designed architecture is set up into the FPGA, and then the embedded software is also downloaded on the evaluation board. Moreover, a ProSLIC device is utilized to interface the SOPC inside the FPGA with an analog telephone. This ProSLIC device contains a few additional capabilities, and it is supplied by Silicon Labs with a handy evaluation board. The prototype is tested with a SIP-based telephone and a SIP proxy server inside the Ericsson Enterprise network. The SIP signaling and the transmission of voice packets is confirmed and proven correct.
Source: Lulea University of Technology
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