As the speed in digital design increases, the design will be more affected by analog issues i.e. inductive and capacitive crosstalk. This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node.It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre…
Contents
1 Introduction
1.1 Purpose
1.2 Reading guidelines
1.3 Abbreviations
2 Sampling Theory
2.1 Basics of sampling
2.1.1 Sampling theorem
2.1.2 Bandpass sampling
2.1.3 Aliasing
2.1.4 Periodic sampling
2.2 Real time sampling
2.3 Time equivalent sampling
2.4 Topologies of digital oscilloscopes off-chip
2.4.1 DSO topology
2.4.2 Sampling oscilloscope topology
3 System Description
3.1 Alternative system architectures
3.1.1 System with on-chip Sampling Clock Generator
3.1.2 System with External Sample Clock Generation
3.1.3 System selection and motivation
3.2 Sampling frequency in periodic sampling
3.2.1 Requirements on sampling frequency
3.2.2 Requirements on practical sampling frequency
3.3 Simulation
3.3.1 Simulation setup
3.3.2 Simulation results
4 Architectures and building blocks
4.1 Track-and-hold circuits
4.2 Master and Slave sampler
4.3 Source follower
4.4 Switch structures
4.4.1 NMOS switch
4.4.2 PMOS switch
4.4.3 Clock feed through and channel charge injection
4.4.4 Transmission-gate switch
4.4.5 Dummy transistor
4.4.6 Linearized switch
4.4.7 Bootstrap switch
Design and implementation
5.1 Requirements
5.2 The DSO and sampling oscilloscope on-chip
5.2.1 Architecture example – sampling oscilloscope on-chip
5.2.2 Architecture example – DSO on-chip
5.2.3 Motivation of selected architecture
5.3 Implementation plan
5.3.1 Voltage range and input buffer
5.3.2 Master switch
5.3.3 Master buffer
5.3.4 Slave switch
5.3.5 Slave buffer
5.4 Implementation
5.4.1 Slave buffer
5.4.2 Integration slave switch – slave buffer
5.4.3 Integration master buffer – slave switch – slave buffer
5.4.4 Integration master switch – master buffer – slave switch – slave buffer
5.4.5 Integration voltage divider – input buffer – master switch – master buffer – slave switch – slave buffer
6 Results and discussion
6.1 Input capacitance vs. bandwidth
6.1.1 1:1 ratio
6.1.2 5:1 ratio
6.2 Sampling example
6.3 Conclusions
6.4 Personal reflections
6.4.1 Future improvements
7 References
Appendix A: Simulation Parameters
Author: Stridfelt, Arvid
Source: Linköping University
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