Reduction of Substrate Noise in Mixed-Signal Circuits

In numerous consumer items, e.g., mobile phones and portable computers, both digital and analog circuits are required. These days, it is easy to implement a sizable subsystem or even a complete system, that earlier required a number of chips, on a single chip. A system on chip (SoC) has usually the benefits of reduced electricity consumption and a reduced fabrication price in contrast to multi-chip solutions. The switching of electronic circuits produces noise that is injected into the silicon substrate. This noise is recognized as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the efficiency of the circuit. This is a significant design issue in mixed-signal ICs where analog and digital circuits share the same substrate.A pair of new sound lowering approaches are suggested in this dissertation work. The initial focuses on lowering the switching noise produced in digital clock buffers. The strategy is to use a clock with long rise and fall times along with a unique D flip-flop. It relaxes the constraints on the clock distribution net, that also lessen the design effort. A sound reduction up to 50% is obtained by using the method. The calculated electricity usage of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The related surge in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers.The next noise lowering strategy concentrates on lowering parallel switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to apply circuits which have as close to periodic power supply currents as possible to obtain low parallel switching noise below the clock in the frequency domain. For this reason we employ precharged differential cascode switch logic plus a novel D flip-flop. To observe the process a couple of pipelined adders have been implemented on transistor level in a 0.13 µm CMOS technology, where the novel circuit is implemented with our technique and the reference circuit with static CMOS logic along with a TSPC D flip-flop. Based on simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB making use of the suggested strategy. The cost is mainly an increase in power usage of almost a factor of 3.Comparisons between substrate coupling in silicon-on-insulator (SOI) and standard bulk technology are made using simple models. Introducing a guard band resulted in an increased attenuation of substrate noise

1 Introduction
1.1 Motivation
1.1.1 Substrate Noise in Mixed-Signal ICs
1.1.2 Representation of Integers in Digital Circuits
1.2 Contributions
1.3 Publications
1.4 Thesis Outline
2 Substrate Noise in Mixed-Signal Circuits
2.1 Substrate Noise
2.2 Substrate Types in CMOS Technologies

2.3 Substrate Modeling
2.3.1 A Substrate Model Derived from Maxwell’s Equations
2.3.2 Substrate Modeling with FEMLAB
2.4 Simultaneous Switching Noise
2.4.1 Cause of Simultaneous Switching Noise
2.4.2 Switching of an On-Chip Load
2.4.3 Switching of an Off-Chip Load
2.4.4 Modeling of Power-Supply Lines
2.5 Inductance in Power Supply Lines
2.6 Injection of Digital Switching Noise
2.6.1 Injection via Substrate Contacts
Substrate Noise in Mixed-Signal Circuits
2.6.2 Injection via Capacitive Coupling of PN-Junctions
2.6.3 Injection via Impact Ionization
2.6.4 Injection via Capacitive Coupling of Interconnects
2.7 Reception of Substrate Noise
2.7.1 Reception via Substrate Contacts and Capacitive Couplings
2.7.2 Body Effect of MOSFET Transistors
2.7.3 Effects of Substrate Noise on Analog Circuits
3 Noise Reduction Methods
3.1 Reduction of Digital Switching Noise
3.1.1 Multiple Power Supply Interconnects
3.1.2 Double Bonding
3.1.3 On-Chip Decoupling
3.1.4 Reduction of Main Peak in Power Supply Impedance
3.1.5 Reduced Supply Bounce CMOS Logic
3.1.6 Clock Skew
3.1.7 Modulation of Clock Frequency
3.1.8 Timing and Sizing of Output Buffers
3.1.9 Reduced Power Supply Voltage
3.1.10 Reduced Package Impedance
3.1.11 Constant Current Logic
3.1.12 Asynchronous Circuits
3.2 Reduction of Coupling
3.2.1 Separate Power Supply Lines
3.2.2 Separate Packages
3.2.3 Multi-Chip Module and System-in-Package
3.2.4 Distance
3.2.5 Floorplanning
3.2.6 Silicon-on-Insulator
3.2.7 Guard Band
3.2.8 Active Guard Band
3.2.9 Deep Trench Isolation
3.3 Reduction of Sensitivity to Substrate Noise
3.4 Planning in Frequency and Time Domain
3.4.1 Frequency Planning
3.4.2 Planning of Switching Events
3.5 Reduction of Noise on Printed Circuit Board
3.5.1 Off-chip Decoupling
3.5.2 Minimizing Off-Chip Inductance
3.5.3 Power Planes and Buried Capacitance on PCB
3.5.4 Low Voltage Differential Signaling
4 Digit Representations in Digital Circuits
4.1 Digit Representations….

Source: Linköping University

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